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<title>MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values </title></head>
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<h1>MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 28 /r MOVAPD xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move aligned packed double-precision floating-point values from xmm2/mem to xmm1.</td></tr>
<tr>
<td>66 0F 29 /r MOVAPD xmm2/m128, xmm1</td>
<td>MR</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move aligned packed double-precision floating-point values from xmm1 to xmm2/mem.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed double-precision floating-point values from xmm2/mem to xmm1.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 29 /r VMOVAPD xmm2/m128, xmm1</td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed double-precision floating-point values from xmm1 to xmm2/mem.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 28 /r VMOVAPD ymm1, ymm2/m256</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed double-precision floating-point values from ymm2/mem to ymm1.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 29 /r VMOVAPD ymm2/m256, ymm1</td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed double-precision floating-point values from ymm1 to ymm2/mem.</td></tr>
<tr>
<td>EVEX.128.66.0F.W1 28 /r VMOVAPD xmm1 {k1}{z}, xmm2/m128</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed double-precision floating-point values from xmm2/m128 to xmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W1 28 /r VMOVAPD ymm1 {k1}{z}, ymm2/m256</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed double-precision floating-point values from ymm2/m256 to ymm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W1 28 /r VMOVAPD zmm1 {k1}{z}, zmm2/m512</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move aligned packed double-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F.W1 29 /r VMOVAPD xmm2/m128 {k1}{z}, xmm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed double-precision floating-point values from xmm1 to xmm2/m128 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W1 29 /r VMOVAPD ymm2/m256 {k1}{z}, ymm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed double-precision floating-point values from ymm1 to ymm2/m256 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W1 29 /r VMOVAPD zmm2/m512 {k1}{z}, zmm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move aligned packed double-precision floating-point values from zmm1 to zmm2/m512 using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FVM-RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FVM-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Moves 2, 4 or 8 double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit, 256-bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit or 512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.</p>
<p>When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit versions), 32-byte (256-bit version) or 64-byte (EVEX.512 encoded version) boundary or a general-protection exception (#GP) will be generated. For EVEX encoded versions, the operand must be aligned to the size of the memory operand. To move double-precision floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
<p>EVEX.512 encoded version:</p>
<p>Moves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float64 memory location, to store the contents of a ZMM register into a 512-bit float64 memory location, or to move data between two ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.</p>
<p>VEX.256 and EVEX.256 encoded versions:</p>
<p>Moves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary or a general-protection exception (#GP) will be generated. To move double-precision floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.</p>
<p>128-bit versions:</p>
<p>Moves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.</p>
<p>128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain unchanged.</p>
<p>(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register destination are zeroed.</p>
<p><strong>Operation</strong></p>
<p><strong>VMOVAPD (EVEX encoded versions, register-copy form)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) SRC[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE  DEST[i+63:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVAPD (EVEX encoded versions, store-form)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i](cid:197) SRC[i+63:i]</p>
<p>ELSE</p>
<p>ELSE *DEST[i+63:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p><strong>VMOVAPD (EVEX encoded versions, load-form)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) SRC[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE  DEST[i+63:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVAPD (VEX.256 encoded version, load - and register copy)</strong></p>
<p>DEST[255:0] (cid:197) SRC[255:0]</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VMOVAPD (VEX.256 encoded version, store-form)</strong></p>
<p>DEST[255:0] (cid:197) SRC[255:0]</p>
<p><strong>VMOVAPD (VEX.128 encoded version, load - and register copy)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>MOVAPD (128-bit load- and register-copy- form Legacy SSE version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>(V)MOVAPD (128-bit store-form version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VMOVAPD __m512d _mm512_load_pd( void * m);</p>
<p>VMOVAPD __m512d _mm512_mask_load_pd(__m512d s, __mmask8 k, void * m);</p>
<p>VMOVAPD __m512d _mm512_maskz_load_pd( __mmask8 k, void * m);</p>
<p>VMOVAPD void _mm512_store_pd( void * d, __m512d a);</p>
<p>VMOVAPD void _mm512_mask_store_pd( void * d, __mmask8 k, __m512d a);</p>
<p>VMOVAPD __m256d _mm256_mask_load_pd(__m256d s, __mmask8 k, void * m);</p>
<p>VMOVAPD __m256d _mm256_maskz_load_pd( __mmask8 k, void * m);</p>
<p>VMOVAPD void _mm256_mask_store_pd( void * d, __mmask8 k, __m256d a);</p>
<p>VMOVAPD __m128d _mm_mask_load_pd(__m128d s, __mmask8 k, void * m);</p>
<p>VMOVAPD __m128d _mm_maskz_load_pd( __mmask8 k, void * m);</p>
<p>VMOVAPD void _mm_mask_store_pd( void * d, __mmask8 k, __m128d a);</p>
<p>MOVAPD __m256d _mm256_load_pd (double * p);</p>
<p>MOVAPD void _mm256_store_pd(double * p, __m256d a);</p>
<p>MOVAPD __m128d _mm_load_pd (double * p);</p>
<p>MOVAPD void _mm_store_pd(double * p, __m128d a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;</p>
<table>
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E1.</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.</td></tr></table></body></html>